Decision feedback equalizer with two's complement computation sharing multiplication
نویسندگان
چکیده
We present an architecture of a high performance decision feedback equalizer based on a computation sharing multiplier. The computation sharing multiplier (CSHMR) uses a redundant number scheme and targets removal of computational redundancy by computation re-use. Use of CSHMR leads to high performance FIR filtering operation by re-using optimal precomputations. A decision feedback equalizer (DFE) implementation based on CSHMR in a 0.35 technology shows 34% improvement in the operating speed over DFE using Wallace tree multiplier.
منابع مشابه
Fast Computation of Compound Expressions in Two's Complement Notation
In this paper we investigate complex (compound) instructions that could provide performance improvement for embedded systems if implemented in hardware. In particular we show that some data dependencies can be captured by the expression (A B) C D. Consequently, assuming two's complement representation, we propose two schemes for the implementation of such an expression. The first scheme is a di...
متن کاملA 125 MHz Digital Equalizer for Broadband Communications
A 125 MHz digital equalizer has been designed based on a 0.25 μm CMOS standard cell library. Partially conforming to the Gigabit Ethernet 1000Base-T standard, the equalizer includes a 16-tap feed-forward adaptive FIR filters accepting 8-bit input, and a 16-tap decision-feedback adaptive FIR filters producing 5-level output symbols. The modified Booth encoding and Wallace tree compression scheme...
متن کاملEecient Integer Multiplication Overrow Detection Circuits
Multiplication of two n-bit integers produces a 2n-bit product. To allow the result to be stored in the same format as the inputs, many processors return the n least signiicant bits of the product and an overrow ag. This paper describes methods for integer multiplication with overrow detection for unsigned and two's complement numbers. A method for combining unsigned and two's complement intege...
متن کاملMfa Mfa Mfa Mfa Mfa Mfa Mfa Mfa Mfa Mfa Mfa Mfa Mfa Mfa Mfa Mfa Mfa Mfa Mfa Mfa Mfa Mfa
100 Integer Multiplication with Over ow Detection or Saturation Michael J. Schulte, Pablo I. Balzola, Ahmet Akkas, and Robert W. Brocato Abstract|High-speed multiplication is frequently used in general-purpose and application-speci c computer systems. These systems often support integer multiplication, where two n-bit integers are multiplied to produce a 2n-bit product. To prevent growth in wor...
متن کاملOptical multiplication and division using modified -signed -digit symbolic substitution
CONTENTS 1. Introduction 2. Symbolic substitution (SS) rules for modified-signed-digit (MSD) addition and subtraction 3. Optical implementation of SS rules 4. Parallel MSD multiplication 4.1. MSD multiplication algorithm 4.2. Optical implementation of the MSD multiplication 5. MSD convergence division 6. Conversion between binary and MSD representations 6.1. From binary code to MSD code 6.2. Fr...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2001